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PDF SC2598 Data sheet ( Hoja de datos )

Número de pieza SC2598
Descripción Low Voltage DDR Termination Regulator
Fabricantes Semtech 
Logotipo Semtech Logotipo



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No Preview Available ! SC2598 Hoja de datos, Descripción, Manual

POWER MANAGEMENT
Features
Input to linear regulator (VIN): 1.0V to 3.6V
Output (VTT): 0.5V to 1.8V
Bias Voltage (VDD): 2.35V to 3.6V
Up to 3A sink or source from VTT for DDR through
DDR4
+ 1% over temperature (with respect to VDDQ/2, in-
cluding internal resistor divider variation) VREF and
VTT
Logic-level enable input
Built in soft-start
Thermal shutdown with auto-restart
Over current protection
Minimal output capacitance
Package: SOIC8-EDP
Applications
DDR Memory Termination
SC2598
Low Voltage DDR
Termination Regulator
Description
The SC2598 is designed to meet the latest JEDEC specifi-
cation for low power DDR3 and DDR4, while also support-
ing DDR and DDR2. The SC2598 regulates up to + 3A for
VTT and up to + 40mA for VREF.
The SC2598 also provides an accuracy of +1% over tem-
perature (which takes into account the internal resistor
divider) for VREF and VTT for the memory controller and
DRAM.
SC2598 protection features include thermal shutdown
with auto-restart for VTT and over-current limit for both
VTT and VREF.
Under-Voltage-Lock-Out circuits are included to ensure
that the output is off when the bias voltage falls below its
threshold, and that the part behaves elegantly in power-
up or power-down.
The low external parts count combined with industry
leading specifications make SC2598 an attractive solution
for DDR through DDR4 termination.
Typical Application Circuit
C VDD
1 μF
C IN
2 x 1 0μF
Rev. 2.0
VDDQ
VDD VIN
VDDQ
VTT
VTTS
VREF
EN GND
C VREF (1)
0 .1 μF
Note:
(1) This component is optional.
© 2015 Semtech Corporation
CVTT
3 x1 0 μF
1

1 page




SC2598 pdf
SC2598
Block Diagram
VDD
6
EN 2
UVLO
VDDQ
5
R
R
Therm al
Shutdow n
S o ft-S ta rt
+
-
D R IVER
LO G IC
7 VIN
8 VTT
1 GND
VREF
4
EN\
3 VTTS
Pin Descriptions
Pin #
Pin Name Pin Function
1
GND
Ground reference for the IC.
Logic input to enable or disable the VTT output. If EN pin is grounded to shut down the linear regulator,
2 EN VREF remains active.
3
VTTS
VTT output sense input. Connect VTTS to the output at the output capacitor to implement remote sense.
4
VREF
The reference output, equal to one half of VDDQ. Connect a 100nF capacitor from this pin to GND.
5
VDDQ
External reference input; range 1V to 3.6V.
6 VDD Input bias voltage — 2.35V to 3.6V . Connect a ceramic capacitor from this pin to GND.
7 VIN LDO input range — 1V to 3.6V. Connect ceramic capacitors from this pin to GND.
8 VTT Output of the linear regulator. Connect ceramic capacitors from this pin to GND.
Thermal pad. Not electrically connected. Connect to the GND plane using multiple vias for optimal heat
PAD NC
sinking.
5

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SC2598 arduino
Outline Drawing — SOIC8-EDP
SC2598
11

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PáginasTotal 13 Páginas
PDF Descargar[ Datasheet SC2598.PDF ]




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