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A3R1GE4EGF
1Gb DDRII Synchronous DRAM
1Gb DDRII SDRAM Specification
A3R1GE4EGF
Zentel Electronics Corp.
Revision 1.0
Apr., 2010
1 page  
CONTENTS
A3R1GE4EGF
1Gb DDRII Synchronous DRAM
Specifications ................................................................................................................................ 1
Features ........................................................................................................................................ 1
Ordering Information ..................................................................................................................... 2
Part Number.................................................................................................................................. 2
Pin Configurations......................................................................................................................... 3
Electrical Specifications................................................................................................................. 5
Block Diagram............................................................................................................................... 25
Pin Function .................................................................................................................................. 26
Command Operation..................................................................................................................... 28
Simplified State Diagram............................................................................................................... 36
Operation of DDR2 SDRAM.......................................................................................................... 37
Revision 1.0
Page 4 / 76
Apr., 2010
5 Page 
A3R1GE4EGF
1Gb DDRII Synchronous DRAM
AC Timing for IDD Test Conditions
For purposes of IDD testing, the following parameters are to be utilized.
Parameter
CL(IDD)
tRCD(IDD)
tRC(IDD)
tRRD(IDD)
tFAW(IDD)
tCK(IDD)
tRAS(min.)(IDD)
tRAS(max.)(IDD)
tRP(IDD)
tRFC(IDD)
DDR2-800
5-5-5
5
12.5
57.5
10
45
2.5
45
70000
12.5
127.5
DDR2-667
5-5-5
5
15
60
10
50
3
45
70000
15
127.5
Unit
tCK
ns
ns
ns
ns
ns
ns
ns
ns
IDD7 Timing Patterns for 8Banks
The detailed timing are shown in the IDD7 Timing Patterns for 8 Banks tables
[x16 organization]
speed bins
Timing Patterns
DDR2-667
DDR2-800
A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D
DD
A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D D
D
Remark: A=Active. RA=Read with auto precharge. D=Deselect
Notes: 1. All banks are being interleaved at minimum tRC(IDD) without violating tRRD (IDD) and tFAW
(IDD) using a Burst length = 4.
2. Control and address bus inputs are STABLE during DESELECTs.
3. IOUT = 0 mA
Revision 1.0
Page 10 / 76
Apr., 2010
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